| 1. Hardware Description | |||
| 1. Hardware description languages.mp4 | 6.61 MB | ||
| 2. Digital systems.mp4 | 3.99 MB | ||
| 3. Levels of abstraction.mp4 | 6.34 MB | ||
| 4. Gate level.mp4 | 4.95 MB | ||
| 5. Register-transfer level.mp4 | 6.9 MB | ||
| 2. Basic Verilog Syntax | |||
| 1. Verilog modules.mp4 | 6.74 MB | ||
| 10. Boolean algebra expressions.mp4 | 1.73 MB | ||
| 11. Continuous assignments.mp4 | 4.78 MB | ||
| 12. Blocking assignments.mp4 | 7.38 MB | ||
| 13. Nonblocking assignments.mp4 | 8.09 MB | ||
| 14. Challenge From schematic to code.mp4 | 4.92 MB | ||
| 15. Solution From schematic to code.mp4 | 10.41 MB | ||
| 2. Instantiating modules.mp4 | 10.31 MB | ||
| 3. Gates and primitives.mp4 | 4.64 MB | ||
| 4. Registers and wires.mp4 | 2.96 MB | ||
| 5. Range specification.mp4 | 8.47 MB | ||
| 6. Numbers and constants.mp4 | 8.86 MB | ||
| 7. Always blocks.mp4 | 1.78 MB | ||
| 8. The if-else statement.mp4 | 3.96 MB | ||
| 9. Case statements.mp4 | 4.62 MB | ||
| 3. Simulation | |||
| 1. Simulation basics.mp4 | 1.75 MB | ||
| 10. Solution You run the show.mp4 | 3.96 MB | ||
| 2. Test bench modules.mp4 | 5.79 MB | ||
| 3. Stimulus variables.mp4 | 2.2 MB | ||
| 4. Clock generation.mp4 | 1.69 MB | ||
| 5. Initial and always blocks.mp4 | 6.42 MB | ||
| 6. A simple simulation.mp4 | 8.13 MB | ||
| 7. Timing directives.mp4 | 5.06 MB | ||
| 8. Display tasks.mp4 | 6.45 MB | ||
| 9. Challenge You run the show.mp4 | 5.08 MB | ||
| 4. Combinational Systems | |||
| 1. Arithmetic and logic operators.mp4 | 5.86 MB | ||
| 2. Challenge Make a 4-bit arithmetic logic unit (ALU).mp4 | 4.02 MB | ||
| 3. Solution Make a 4-bit arithmetic logic unit (ALU).mp4 | 5.71 MB | ||
| 4. Getting your ALU on a field-programmable gate array (FPGA).mp4 | 11.79 MB | ||
| 5. A functional demo of the ALU.mp4 | 33.33 MB | ||
| 5. Sequential Systems | |||
| 1. Flip-flops.mp4 | 5.9 MB | ||
| 2. Edge sensitivity.mp4 | 4.82 MB | ||
| 3. A shift register example.mp4 | 8.6 MB | ||
| 4. Challenge Make a clock divider.mp4 | 4.25 MB | ||
| 5. Solution Make a clock divider.mp4 | 6.85 MB | ||
| 6. Getting your clock divider on an FPGA.mp4 | 8.24 MB | ||
| 7. A functional demo of the clock divider.mp4 | 18.2 MB | ||
| Conclusion | |||
| 1. Next steps.mp4 | 3.09 MB | ||
| Introduction | |||
| 1. Verilog Your key to digital design.mp4 | 6.56 MB | ||
| 2. What you should know.mp4 | 1.31 MB | ||
| 3. Setting up your environment.mp4 | 9.12 MB |
FPGA development requires a big switch from more typical programming processes. In order to get an FPGA-based embedded system up and running, developers must add a hardware description language to their repertoire. In this course, Eduardo Corpeño helps you learn the fundamentals of one such language: the popular and concise Verilog. Eduardo begins with the basics; he explains what a hardware description language is and some similarities to traditional programming languages. He then covers the basic syntax of Verilog, as well as how to create test bench modules to run simulations, use variables with operators as an advantage of the behavioral level of abstraction, and more. Along the way, he provides demos and programming challenges that allow you to put your new skills to the test.
Learning objectives
1. The purpose of hardware description languages
2. The different abstraction levels of a digital system
3. The structure and syntax of a module in Verilog
4. The uses of range specification
5. If-else statements
6. Boolean expressions
7. The nature and limitations of simulations
8. Combinational and sequential systems
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