Raleva K. Modeling Self-Heating Effects in Nanoscale Devices 2017

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For the last half-century, miniaturization of integrated circuits through transistor scaling has been the driving force for the semiconductor technology roadmap.
The idea of a technology roadmap for semiconductors can be traced back to a paper by Gordon Moore published in 1965, in which he predicted that the number f transistors in a semiconductor chip will double every 18 to 24 months. This consequently results in a reduction of the cost per elementary function (cost per bit for memory devices, or cost per MIPS for computing devices), thus enabling the production of more complex circuits on a single semiconductor substrate. This trend towards miniaturization is known as ‘Moore’s Law’.
For several decades, the ability of the semiconductor industry to follow Moore’s law has been the engine of an incredible cycle: through transistor scaling one obtains a better performance-to-cost ratio for integrated circuits (ICs), which has resulted in an exponential growth of the semiconductor market. This, in turn, allows further investments in new technologies which enable further scaling. Scaling in turn, enables creation of more complex, faster, cheaper and low-power ICs
Preface
Introduction
Current state of the art in modeling heating effects in nanoscale devices
Phonon Monte Carlo simulation
Summary
Appendix A: Derivation of energy balance equations for acoustic and optical phonons