Tan S. Long-Term Reliability of Nanometer VLSI Systems...2019

Textbook in PDF format

Reviews classic Electromigration (EM) models, as well as existing EM failure models and discusses the limitations of those models.
Introduces a dynamic EM model to address transient stress evolution, in which wires are stressed under time-varying current flows, and the EM recovery effects. Also includes new, parameterized equivalent DC current based EM models to address the recovery and transient effects.
Presents a cross-layer approach to transistor aging modeling, analysis and mitigation, spanning multiple abstraction levels.
Equips readers for EM-induced dynamic reliability management and energy or lifetime optimization techniques, for many-core dark silicon microprocessors, embedded systems, lower power many-core processors and datacenters.
Physics-Based EM Analysis and System-Level Dynamic Reliability Management.
Introduction.
Physics-Based EM Modeling.
Fast EM Stress Evolution Analysis Using Krylov Subspace Method.
Fast EM Immortality Analysis for Multi-Segment Copper Interconnect Wires.
Dynamic EM Models for Transient Stress Evolution and Recovery.
Compact EM Models for Multi-Segment Interconnect Wires.
EM Assessment for Power Grid Networks.
Resource-Based EM Modeling DRM for Multi-Core Microprocessors.
DRM and Optimization for Real-Time Embedded Systems.
Learning-Based DRM and Energy Optimization for Manycore Dark Silicon Processors.
Recovery-Aware DRM for Near-Threshold Dark Silicon Processors.
Cross-Layer DRM and Optimization for Datacenter Systems.
Transistor Aging Effects and Reliability.
Introduction.
Aging-Aware Timing Analysis.
Aging-Aware Standard Cell Library Optimization Methods.
Aging Effects in Sequential Elements.
Aging Guardband Reduction Through Selective Flip-Flop Optimization.
Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical Flip-Flops.
Aging Relaxation at Microarchitecture Level Using Special NOPs.
ExtraTime: Modeling and Analysis of Transistor Aging at Microarchitecture-Level.
Reducing Processor Wearout by Exploiting the Timing Slack of Instructions.
Index