| 1. Basic Concepts of Digital.mp4 | 19.3 MB | ||
| 1. Basic Concepts of Digital.srt | 1.8 KB | ||
| 1. Digital Design Flow.mp4 | 28.2 MB | ||
| 1. Digital Design Flow.srt | 4.4 KB | ||
| 1. Interface, Intity.mp4 | 8.2 MB | ||
| 1. Interface, Intity.srt | 2.1 KB | ||
| 1. Uses of VHDL.mp4 | 18.6 MB | ||
| 1. Uses of VHDL.srt | 2.3 KB | ||
| 10. ISE Software Area.mp4 | 26.8 MB | ||
| 10. ISE Software Area.srt | 4.5 KB | ||
| 10. SR Latch.mp4 | 13.1 MB | ||
| 10. SR Latch.srt | 2 KB | ||
| 10. Simulation.mp4 | 28.2 MB | ||
| 10. Simulation.srt | 3.2 KB | ||
| 11. Changing the names of the signals.mp4 | 130.4 MB | ||
| 11. Changing the names of the signals.srt | 12.6 KB | ||
| 11. New Source Wizard.mp4 | 33.1 MB | ||
| 11. New Source Wizard.srt | 3.9 KB | ||
| 11. SR Latch.mp4 | 22.6 MB | ||
| 11. SR Latch.srt | 4.2 KB | ||
| 12. ISE Design properties.mp4 | 43.9 MB | ||
| 12. ISE Design properties.srt | 4.2 KB | ||
| 12. Port mapping.mp4 | 24.9 MB | ||
| 12. Port mapping.srt | 2.4 KB | ||
| 12. SR Latch.mp4 | 30.4 MB | ||
| 12. SR Latch.srt | 5 KB | ||
| 13. Performing in the input.mp4 | 14.8 MB | ||
| 13. Performing in the input.srt | 1.6 KB | ||
| 13. SR Latch.mp4 | 30 MB | ||
| 13. SR Latch.srt | 4.2 KB | ||
| 13. Synthesize.mp4 | 44.3 MB | ||
| 13. Synthesize.srt | 4 KB | ||
| 14. BCD code to Excess-3.mp4 | 58.3 MB | ||
| 14. BCD code to Excess-3.srt | 819.2 B | ||
| 14. ISE Schematic.mp4 | 46.5 MB | ||
| 14. ISE Schematic.srt | 4.4 KB | ||
| 14. SR Latch.mp4 | 18.8 MB | ||
| 14. SR Latch.srt | 2.3 KB | ||
| 15. ISE Signals.mp4 | 44.2 MB | ||
| 15. ISE Signals.srt | 3.6 KB | ||
| 15. SR Latch.mp4 | 8.5 MB | ||
| 15. SR Latch.srt | 1.1 KB | ||
| 15. Simulation Example.mp4 | 11.2 MB | ||
| 15. Simulation Example.srt | 921.6 B | ||
| 16. Demultiplexter.mp4 | 96.7 MB | ||
| 16. Demultiplexter.srt | 7.1 KB | ||
| 16. ISE warnings.mp4 | 54.6 MB | ||
| 16. ISE warnings.srt | 4.8 KB | ||
| 16. SR Latch.mp4 | 22.5 MB | ||
| 16. SR Latch.srt | 4.2 KB | ||
| 17. D latch.mp4 | 34.2 MB | ||
| 17. D latch.srt | 3.9 KB | ||
| 17. SR Latch.mp4 | 8.3 MB | ||
| 17. SR Latch.srt | 1.1 KB | ||
| 18. Seneric inside NTT.mp4 | 124.1 MB | ||
| 18. Seneric inside NTT.srt | 11.2 KB | ||
| 18. Timing Diagram.mp4 | 24.4 MB | ||
| 18. Timing Diagram.srt | 4.9 KB | ||
| 19. SR Latch Timing Diagram.mp4 | 11.6 MB | ||
| 19. SR Latch Timing Diagram.srt | 2.3 KB | ||
| 19. Simulation Example.mp4 | 33.9 MB | ||
| 19. Simulation Example.srt | 3 KB | ||
| 2. ASIC Digital Flow.mp4 | 33 MB | ||
| 2. ASIC Digital Flow.srt | 4.8 KB | ||
| 2. Basic Concepts of Digital.mp4 | 42.9 MB | ||
| 2. Basic Concepts of Digital.srt | 4.8 KB | ||
| 2. Before we start.mp4 | 15.9 MB | ||
| 2. Before we start.srt | 2.1 KB | ||
| 2. Ports in VHDL.mp4 | 12.8 MB | ||
| 2. Ports in VHDL.srt | 3.3 KB | ||
| 20. Propagation.mp4 | 30.2 MB | ||
| 20. Propagation.srt | 3.5 KB | ||
| 20. SR Latch State Diagram.mp4 | 27.5 MB | ||
| 20. SR Latch State Diagram.srt | 6.2 KB | ||
| 21. Generic Example.mp4 | 71.6 MB | ||
| 21. Generic Example.srt | 7.2 KB | ||
| 21. SR Latch.mp4 | 21.6 MB | ||
| 21. SR Latch.srt | 6.2 KB | ||
| 22. ISE Library Section.mp4 | 70.1 MB | ||
| 22. ISE Library Section.srt | 7 KB | ||
| 22. SR Latch with Enable.mp4 | 17.4 MB | ||
| 22. SR Latch with Enable.srt | 3.7 KB | ||
| 23. D Latch.mp4 | 24.6 MB | ||
| 23. D Latch.srt | 4.4 KB | ||
| 23. Herarchial and External Naming.mp4 | 35.7 MB | ||
| 23. Herarchial and External Naming.srt | 4.3 KB | ||
| 24. D Latch Timing Diagram.mp4 | 15.7 MB | ||
| 24. D Latch Timing Diagram.srt | 4.5 KB | ||
| 24. Type conversions.mp4 | 29.8 MB | ||
| 24. Type conversions.srt | 4 KB | ||
| 25. D Latch characteristic.mp4 | 20.5 MB | ||
| 25. D Latch characteristic.srt | 4.1 KB | ||
| 25. Type Conversion Chart.mp4 | 23.1 MB | ||
| 25. Type Conversion Chart.srt | 2.6 KB | ||
| 26. D Latch with transmission gate.mp4 | 9.8 MB | ||
| 26. D Latch with transmission gate.srt | 2.5 KB | ||
| 26. Type Conversion in ISE.mp4 | 49.1 MB | ||
| 26. Type Conversion in ISE.srt | 3.5 KB | ||
| 27. D Latch with transmission gate.mp4 | 21.9 MB | ||
| 27. D Latch with transmission gate.srt | 4.1 KB | ||
| 27. Type Conversion Simulation.mp4 | 92.9 MB | ||
| 27. Type Conversion Simulation.srt | 9.4 KB | ||
| 28. JK Latch.mp4 | 13.2 MB | ||
| 28. JK Latch.srt | 3.2 KB | ||
| 29. JK Latch.mp4 | 20.3 MB | ||
| 29. JK Latch.srt | 6 KB | ||
| 3. Basic Concepts of Digital.mp4 | 13.2 MB | ||
| 3. Basic Concepts of Digital.srt | 1.5 KB | ||
| 3. Generic.mp4 | 12 MB | ||
| 3. Generic.srt | 3.2 KB | ||
| 3. System Level Digital Flow.mp4 | 7 MB | ||
| 3. System Level Digital Flow.srt | 1.5 KB | ||
| 3. Verilog vs VHDL.mp4 | 20 MB | ||
| 3. Verilog vs VHDL.srt | 2.8 KB | ||
| 30. Flip Flops.mp4 | 18.7 MB | ||
| 30. Flip Flops.srt | 4.1 KB | ||
| 31. Flip Flops.mp4 | 30.1 MB | ||
| 31. Flip Flops.srt | 5 KB | ||
| 32. D Flip Flops.mp4 | 9.1 MB | ||
| 32. D Flip Flops.srt | 2.3 KB | ||
| 33. D Flip Flops.mp4 | 28 MB | ||
| 33. D Flip Flops.srt | 4.8 KB | ||
| 34. D Flip Flops.mp4 | 20.4 MB | ||
| 34. D Flip Flops.srt | 4 KB | ||
| 35. D Flip Flops.mp4 | 17.3 MB | ||
| 35. D Flip Flops.srt | 2.8 KB | ||
| 36. Latch vs Flip Flop.mp4 | 8.4 MB | ||
| 36. Latch vs Flip Flop.srt | 1.2 KB | ||
| 37. Latch vs Flip Flop.mp4 | 22 MB | ||
| 37. Latch vs Flip Flop.srt | 2.8 KB | ||
| 38. Latch vs Flip Flop.mp4 | 25.5 MB | ||
| 38. Latch vs Flip Flop.srt | 3.5 KB | ||
| 39. Rising Edge D-FF.mp4 | 16.2 MB | ||
| 39. Rising Edge D-FF.srt | 4.4 KB | ||
| 4. New Project Wizard.mp4 | 26.3 MB | ||
| 4. New Project Wizard.srt | 2.7 KB | ||
| 4. Reprogammable Devices.mp4 | 21.3 MB | ||
| 4. Reprogammable Devices.srt | 4.8 KB | ||
| 4. Sequential vs combinational.mp4 | 13.2 MB | ||
| 4. Sequential vs combinational.srt | 4.2 KB | ||
| 4. VHDL.mp4 | 4.9 MB | ||
| 4. VHDL.srt | 1.9 KB | ||
| 40. Rising Edge D-FF.mp4 | 21.1 MB | ||
| 40. Rising Edge D-FF.srt | 3.8 KB | ||
| 41. Master Slave FF.mp4 | 23.9 MB | ||
| 41. Master Slave FF.srt | 4.4 KB | ||
| 42. T Flip Flop.mp4 | 13.6 MB | ||
| 42. T Flip Flop.srt | 3.4 KB | ||
| 43. Asynchronous Preset.mp4 | 13.5 MB | ||
| 43. Asynchronous Preset.srt | 3.3 KB | ||
| 44. Synchronous Reset.mp4 | 25.8 MB | ||
| 44. Synchronous Reset.srt | 4.7 KB | ||
| 45. Additional Inputs of Flip Flop.mp4 | 9.4 MB | ||
| 45. Additional Inputs of Flip Flop.srt | 2.7 KB | ||
| 46. Setup time, Hold Time, Delay types.mp4 | 12.7 MB | ||
| 46. Setup time, Hold Time, Delay types.srt | 2.8 KB | ||
| 47. Setup time, Hold Time, Delay types.mp4 | 37 MB | ||
| 47. Setup time, Hold Time, Delay types.srt | 4.5 KB | ||
| 48. Timing Requirements.mp4 | 18.6 MB | ||
| 48. Timing Requirements.srt | 4.8 KB | ||
| 49. Timing Requirements.mp4 | 9.2 MB | ||
| 49. Timing Requirements.srt | 1.6 KB | ||
| 5. Common Components.mp4 | 16.6 MB | ||
| 5. Common Components.srt | 2.1 KB | ||
| 5. Sequential vs combinational.mp4 | 9 MB | ||
| 5. Sequential vs combinational.srt | 2.3 KB | ||
| 5. Synchronizing.mp4 | 34.9 MB | ||
| 5. Synchronizing.srt | 2.9 KB | ||
| 50. Timing Requirements.mp4 | 35.8 MB | ||
| 50. Timing Requirements.srt | 5 KB | ||
| 51. Timing Requirements.mp4 | 21.4 MB | ||
| 51. Timing Requirements.srt | 3.7 KB | ||
| 52. Synchronous vs Asynchronous.mp4 | 48.5 MB | ||
| 52. Synchronous vs Asynchronous.srt | 6 KB | ||
| 53. Clock Signals.mp4 | 9.1 MB | ||
| 53. Clock Signals.srt | 1.6 KB | ||
| 54. Synchronous circuits.mp4 | 17.6 MB | ||
| 54. Synchronous circuits.srt | 4.2 KB | ||
| 55. Sequential circuit analysis.mp4 | 6.2 MB | ||
| 55. Sequential circuit analysis.srt | 1.1 KB | ||
| 56. Sequential circuit.mp4 | 14.2 MB | ||
| 56. Sequential circuit.srt | 2 KB | ||
| 57. Sequential circuit.mp4 | 26.6 MB | ||
| 57. Sequential circuit.srt | 4.8 KB | ||
| 58. Sequential circuit.mp4 | 17.7 MB | ||
| 58. Sequential circuit.srt | 2.5 KB | ||
| 59. Sequential circuit.mp4 | 26 MB | ||
| 59. Sequential circuit.srt | 4.3 KB | ||
| 6. Encoder.mp4 | 8.4 MB | ||
| 6. Encoder.srt | 1.5 KB | ||
| 6. FIFO.mp4 | 21.1 MB | ||
| 6. FIFO.srt | 3.7 KB | ||
| 6. Sequential logic idea.mp4 | 24.6 MB | ||
| 6. Sequential logic idea.srt | 3.9 KB | ||
| 60. Sequential circuit.mp4 | 25.7 MB | ||
| 60. Sequential circuit.srt | 4.9 KB | ||
| 61. State table.mp4 | 16.1 MB | ||
| 61. State table.srt | 2.5 KB | ||
| 62. PLD Family.mp4 | 17 MB | ||
| 62. PLD Family.srt | 3.4 KB | ||
| 63. Mask Programming Devices.mp4 | 8.2 MB | ||
| 63. Mask Programming Devices.srt | 2.2 KB | ||
| 64. PLA.mp4 | 8.2 MB | ||
| 64. PLA.srt | 2.4 KB | ||
| 65. GLA.mp4 | 13.2 MB | ||
| 65. GLA.srt | 1.8 KB | ||
| 66. CPLD.mp4 | 13.2 MB | ||
| 66. CPLD.srt | 1.6 KB | ||
| 67. CPLD IC.mp4 | 22 MB | ||
| 67. CPLD IC.srt | 2.5 KB | ||
| 68. CPLD Architecture.mp4 | 10 MB | ||
| 68. CPLD Architecture.srt | 1.8 KB | ||
| 69. FPGA.mp4 | 18.8 MB | ||
| 69. FPGA.srt | 3.4 KB | ||
| 7. Designing the Gate Level.mp4 | 66.8 MB | ||
| 7. Designing the Gate Level.srt | 4.7 KB | ||
| 7. Sequential logic idea.mp4 | 68.4 MB | ||
| 7. Sequential logic idea.srt | 11.8 KB | ||
| 7. UART.mp4 | 20.2 MB | ||
| 7. UART.srt | 2.9 KB | ||
| 70. FPGA Architecture.mp4 | 8.9 MB | ||
| 70. FPGA Architecture.srt | 2.2 KB | ||
| 71. FPGA Architecture.mp4 | 23.7 MB | ||
| 71. FPGA Architecture.srt | 3.8 KB | ||
| 72. FPGA Architecture.mp4 | 16.1 MB | ||
| 72. FPGA Architecture.srt | 1.5 KB | ||
| 73. FPGA & CPLD Usage.mp4 | 35.7 MB | ||
| 73. FPGA & CPLD Usage.srt | 4 KB | ||
| 74. FPGA, SystemC, Verilog.mp4 | 28.9 MB | ||
| 74. FPGA, SystemC, Verilog.srt | 4 KB | ||
| 75. ISE Install.mp4 | 23.9 MB | ||
| 75. ISE Install.srt | 2.1 KB | ||
| 8. FIFO operation.mp4 | 45.4 MB | ||
| 8. FIFO operation.srt | 3.5 KB | ||
| 8. SR Latch.mp4 | 6.8 MB | ||
| 8. SR Latch.srt | 1.6 KB | ||
| 8. Test Bench.mp4 | 11.5 MB | ||
| 8. Test Bench.srt | 2.7 KB | ||
| 9. General Purpose processor.mp4 | 39.2 MB | ||
| 9. General Purpose processor.srt | 4 KB | ||
| 9. SR Latch.mp4 | 17.5 MB | ||
| 9. SR Latch.srt | 2.5 KB | ||
| 9. Test Bench Types.mp4 | 111.9 MB | ||
| 9. Test Bench Types.srt | 11.2 KB | ||
| Bonus Resources.txt | 307.2 B | ||
| Get Bonus Downloads Here.url | 204.8 B | ||
| ▲ 246 total files | |||
Designing Digital Systems Using VHDL - An introduction
Genre: eLearning | MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz
Language: English | Size: 3.25 GB | Duration: 9h 45m
Build your foundation in digital domain by mastering VHDL and become a Digital Design Engineer - Rahsoft RAHDG432
What you'll learn
Basic Concepts of Digital Electronics
Sequential vs combinational
SR Latch
Flip Flops
PLD Family
FPGA Basics
VHDL Basics
FIFO
ISE Software
Generic
Synchronizing
Test Bench
ISE Simulation
BCD code to Excess-3
Demultiplexer
Hierarchical and External Naming
Description
Description
In RAHDG 432 we’ll Focus on designing different types of digital systems using VHDL language code then we simulate those in the ISE software and at the end we do the implementation. It includes Design and analysis of latches and flip-flops. Number of digital designs have been designed in VHDL language to make you understand them better.
This course describes the different types of design units in VHDL such as entity, architecture, configuration, package and package body. The design and analysis of synchronous state machines. State minimization and introduction to state assignment. Each topic will have many examples which goes over them briefly with different parts. By end of chapter 2 and 4 there will be a quiz for you to test your understanding of that specific chapter.
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