| 1 -Behavior of SRAM and Usage Suggestions.mp4 | 384.8 MB | ||
| 1 -Handshake Interface and Sync_FIFO.mp4 | 199.1 MB | ||
| 1 -Introduction.mp4 | 14.2 MB | ||
| 1 -Pipeline Fundamental.mp4 | 126.5 MB | ||
| 2 -Depth Calculation for FIFO.mp4 | 104.2 MB | ||
| 2 -Pipeline Design Example BIN2BCD.mp4 | 300.7 MB | ||
| Bonus Resources.txt | 409.6 B | ||
| Get Bonus Downloads Here.url | 204.8 B |
Digital IC/FPGA Design P3:Common Used Hardware Architectures
https://DevCourseWeb.com
Published 12/2024
Created by SKY SiliconThink
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Level: All | Genre: eLearning | Language: English | Duration: 6 Lectures ( 2h 39m ) | Size: 1.1 GB
a big step towards complex IP design
What you'll learn
Behavior of SRAM and usage suggestions
Handshake interface and synchronous FIFO
Pipeline to maximal clock frequency
Arbiter
Cross clock domain (CDC) and asynchronous FIFO
Ping-Pong
Pipeline with control (feedback)
Pipeline with hazard and forward path
Slide window
Requirements
Basic knowledge of digital fundamental
Basic C or C++ programing language
Basic Verilog Language
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| 3.3 GB | freecoursewb | 1 week | 25 | 7 | |
| 2 GB | freecoursewb | 3 weeks | 18 | 13 | |
| 267.9 MB | freecoursewb | 3 weeks | 0 | 0 | |
| 2.8 GB | freecoursewb | 1 month | 14 | 9 | |
| 289.4 MB | freecoursewb | 1 month | 11 | 1 |
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