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Udemy - Digital Timing Basics For Vlsi Interview and Soc Design

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Added 3 years ago by freecoursewb in Other
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Udemy - Digital Timing Basics For Vlsi Interview and Soc Design (Size: 825.8 MB)
  1 - Introduction.mp4 29.5 MB
  10 - Setup Time Condition in Cycle Path English.srt 9 KB
  10 - Setup Time Condition in Cycle Path.mp4 24.1 MB
  11 - Hold Time Condition in Cycle Path English.srt 10.1 KB
  11 - Hold Time Condition in Cycle Path.mp4 30.7 MB
  12 - Example for Setup & Hold Condition English.srt 17 KB
  12 - Example for Setup & Hold Condition.mp4 47.7 MB
  13 - Setup & Hold Margin Computation English.srt 7 KB
  13 - Setup & Hold Margin Computation.mp4 18.8 MB
  14 - Setup Violation.mp4 24.5 MB
  15 - Setup Violation Fix Clock Path Delay English.srt 12.8 KB
  15 - Setup Violation Fix Clock Path Delay.mp4 53.6 MB
  16 - Hold Violation English.srt 6.4 KB
  16 - Hold Violation.mp4 14.9 MB
  17 - Hold Violation Fix Data Path Delay English.srt 7 KB
  17 - Hold Violation Fix Data Path Delay.mp4 19.1 MB
  18 - Good Margin but Higher Latency English.srt 8.5 KB
  18 - Good Margin but Higher Latency.mp4 30.3 MB
  19 - Latency Reduction with Optimized Design English.srt 8 KB
  19 - Latency Reduction with Optimized Design.mp4 34.9 MB
  2 - Basic Definitions.mp4 3.8 MB
  20 - Design Issues in Real World SoC English.srt 10.5 KB
  20 - Design Issues in Real World SoC.mp4 18.1 MB
  21 - Positive Latch Setup & Hold Time English.srt 14.2 KB
  21 - Positive Latch Setup & Hold Time.mp4 36.6 MB
  22 - Negative Latch Setup & Hold Time.mp4 23.8 MB
  23 - Clock Gating Setup & Hold Time.mp4 37.8 MB
  24 - Negative Hold Time for Flop English.srt 13.8 KB
  24 - Negative Hold Time for Flop.mp4 35 MB
  25 - Negative Setup Time for Flop English.srt 9.8 KB
  25 - Negative Setup Time for Flop.mp4 26.4 MB
  26 - Setup Hold Clk2Q and Clock Skew English.srt 6.2 KB
  26 - Setup Hold Clk2Q and Clock Skew.mp4 14.1 MB
  27 - Hold Margin with Frequency English.srt 4.7 KB
  27 - Hold Margin with Frequency.mp4 9 MB
  28 - Setup Margin with Frequency English.srt 5.6 KB
  28 - Setup Margin with Frequency.mp4 11.7 MB
  29 - FV Curve Introduction English.srt 7.7 KB
  29 - FV Curve Introduction.mp4 16 MB
  3 - Quick Summary English.srt 6.3 KB
  3 - Quick Summary.mp4 13.5 MB
  30 - FV Curve Explanation English.srt 25.6 KB
  30 - FV Curve Explanation.mp4 66 MB
  31 - Multiple Path Problem Statement.mp4 6.5 MB
  32 - Multiple Path Setup Time Analysis English.srt 5.8 KB
  32 - Multiple Path Setup Time Analysis.mp4 17.4 MB
  33 - Multiple Path Hold Time Analysis English.srt 6.6 KB
  33 - Multiple Path Hold Time Analysis.mp4 17.7 MB
  34 - Multiple Path Summary English.srt 5 KB
  34 - Multiple Path Summary.mp4 13.7 MB
  35 - Frequency of Operation.mp4 9.6 MB
  36 - Minimum Frequency of Operation English.srt 5.3 KB
  36 - Minimum Frequency of Operation.mp4 16.3 MB
  37 - Maximum Frequency of Operation without Clock Skew English.srt 3 KB
  37 - Maximum Frequency of Operation without Clock Skew.mp4 9 MB
  38 - Maximum Frequency of Operation with Clock Skew English.srt 13.5 KB
  38 - Maximum Frequency of Operation with Clock Skew.mp4 38.3 MB
  39 - Next Step English.srt 819.2 B
  39 - Next Step.mp4 3.6 MB
  4 - Setup Time & Setup Margin English.srt 5.2 KB
  4 - Setup Time & Setup Margin.mp4 11.6 MB
  5 - Hold time & Hold Margin English.srt 4.3 KB
  5 - Hold time & Hold Margin.mp4 9 MB
  6 - Clock to Q Delay English.srt 1.9 KB
  6 - Clock to Q Delay.mp4 3.6 MB
  7 - Buffer English.srt 4.8 KB
  7 - Buffer.mp4 11 MB
  8 - Logic Implementation English.srt 1.1 KB
  8 - Logic Implementation.mp4 2.2 MB
  9 - Physical Implementation English.srt 7.6 KB
  9 - Physical Implementation.mp4 16.1 MB
  Bonus Resources.txt 409.6 B
  Get Bonus Downloads Here.url 204.8 B
  ▲ 73 total files

Description


Digital Timing Basics For Vlsi Interview & Soc Design
https://DevCourseWeb.com

MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz
Language: English (US) | Size: 826.03 MB | Duration: 4h 1m

A VLSI Course on Timing Concepts frequently used in Physical Design (Static Timing Analysis - STA), RTL & Circuit Design

What you'll learn
Basics of Flop & Latch Timings
Set-up, Hold, Clock to Q, Clock Skew
Set-up & Hold violation checks
Set-up & Hold violation fixes
Latency Minimization
Set-up & Hold Margin in Digital Ckts
Min & Max Path Analysis
Clock Gating
F-V Curve in SoC

Requirements
Knowledge of Flop functionality will suffice

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