| 1 -Introduction.mp4 | 41.9 MB | ||
| 1 -Vivado Simulation FIR compiler v7.2.mp4 | 311.7 MB | ||
| 1 -Zynq 7000 SoC development C application to interface with FIR compiler IP cores.mp4 | 341.5 MB | ||
| 2 -Requirements and Workflow Automation.mp4 | 115.4 MB | ||
| 2 -Vivado Simulation CIC compiler v4.0.mp4 | 138.4 MB | ||
| 2 -Zynq 7000 SoC development C application to interface with CIC compiler IP cores.mp4 | 298.6 MB | ||
| 3 -Vivado Simulation DDS compiler v6.0.mp4 | 122.5 MB | ||
| 3 -Zynq 7000 SoC development C application to interface with DDS compiler IP cores.mp4 | 224.3 MB | ||
| 4 -Vivado Simulation Fast Fourier Transform v9.1.mp4 | 114.8 MB | ||
| 4 -Zynq 7000 SoC development C application to interface with FFT IP core.mp4 | 255.8 MB | ||
| BPF.coe | 204.8 B | ||
| Bonus Resources.txt | 102.4 B | ||
| Get Bonus Downloads Here.url | 204.8 B | ||
| LPF_dec.coe | 204.8 B | ||
| LPF_int.coe | 204.8 B | ||
| README.md | 2.1 KB | ||
| cic_compiler.py | 3.5 KB | ||
| cic_compiler_tb.v | 3.9 KB | ||
| cic_compiler_tb_behav.wcfg | 4 KB | ||
| cic_hw.tcl | 1.8 KB | ||
| cic_main.c | 6.7 KB | ||
| cic_sys.tcl | 45.9 KB | ||
| clean.py | 1.8 KB | ||
| create_vitis.py | 1.7 KB | ||
| dds_axi_wrapper.v | 2.2 KB | ||
| dds_compiler.py | 4.9 KB | ||
| dds_compiler_tb.v | 5.6 KB | ||
| dds_compiler_tb_behav.wcfg | 20.6 KB | ||
| dds_hw.tcl | 2 KB | ||
| dds_main.c | 7.2 KB | ||
| dds_sys.tcl | 45.7 KB | ||
| dsp_sim.tcl | 13.3 KB | ||
| fir_compiler.py | 4.1 KB | ||
| fir_compiler_tb.v | 7.8 KB | ||
| fir_compiler_tb_behav.wcfg | 11.9 KB | ||
| fir_hw.tcl | 1.7 KB | ||
| fir_main.c | 8.8 KB | ||
| fir_sys.tcl | 47.2 KB | ||
| gui_launcher.py | 2 KB | ||
| hilbert_0.coe | 716.8 B | ||
| run_sim.py | 2.3 KB | ||
| run_vitis.py | 2.7 KB | ||
| run_vivado.py | 2.5 KB | ||
| tb_util.vh | 7.3 KB | ||
| xfft.py | 5.7 KB | ||
| xfft_hw.tcl | 1.7 KB | ||
| xfft_main.c | 9.3 KB | ||
| xfft_sys.tcl | 41.1 KB | ||
| xfft_tb.v | 5.7 KB | ||
| xfft_tb_behav.wcfg | 28.7 KB | ||
| ▲ 50 total files | |||
Mastering Xilinx DSP IP Cores: FIR, CIC, DDS, FFT
https://WebToolTip.com
Published 3/2025
Created by Aleksei Rostov
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Level: Beginner | Genre: eLearning | Language: English | Duration: 10 Lectures ( 2h 17m ) | Size: 1.91 GB
Practical FPGA DSP with Xilinx IP cores (FIR, CIC, DDS, FFT): from simulation to real-time deployment on Zynq 7000
What you'll learn
How to Simulate Xilinx DSP IP cores (FIR, CIC, DDS compiler and FFT) in Vivado with Verilog testbenches & Python analysis
How to Integrate IP cores into FPGA designs on development board
How to Develop standalone embedded C application to interface with DSP IP cores
How to Automate Vivado & Vitis workflow with TCL and Python scripts
Requirements
Vivado 2024.2
Vitis 2024.2
Python >= 3.0
Powershell
Any development board with Zynq 7000 SoC (Arty z7-20 as example)
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