| 1 - Code Access.html | 307.2 B | ||
| 1 - Read This.html | 204.8 B | ||
| 1 - Recommended Setup Using Docker.html | 716.8 B | ||
| 1 - Simulation Only Setup.html | 307.2 B | ||
| 1 -Docker Windows Install (Optional).mp4 | 14 MB | ||
| 1 -EDA Playground Hints (Optional).mp4 | 26.3 MB | ||
| 1 -Introduction.mp4 | 10.2 MB | ||
| 1 -Measure Latency - 1.mp4 | 31.3 MB | ||
| 1 -One-Hot Encoding.mp4 | 8.6 MB | ||
| 1 -RTL GCD.mp4 | 5.5 MB | ||
| 1 -RTL FSM Design Pattern.mp4 | 8.7 MB | ||
| 1 -Wrap Up.mp4 | 13.4 MB | ||
| 2 - Download Docker Image.html | 307.2 B | ||
| 2 - How to use this course.html | 204.8 B | ||
| 2 -Download Docker Image.mp4 | 7.1 MB | ||
| 2 -GCDOne Hot Encoded.mp4 | 25.5 MB | ||
| 2 -Learning Tips (Optional).mp4 | 5.4 MB | ||
| 2 -Measure Latency - 2.mp4 | 26 MB | ||
| 2 -State Definitions.mp4 | 20.9 MB | ||
| 3 - Run Docker with GUI (Windows).html | 819.2 B | ||
| 3 -FSMs in Digital Logic.mp4 | 11.4 MB | ||
| 3 -Fewer States.mp4 | 32.4 MB | ||
| 3 -Run Docker with GUI (Windows).mp4 | 6.7 MB | ||
| 3 -Simulation.mp4 | 4.9 MB | ||
| 3 -Transition Arcs.mp4 | 16.8 MB | ||
| 4 - Run Docker with GUI (Linux - Ubuntu).html | 307.2 B | ||
| 4 - Run Docker with GUI (Mac OS).html | 716.8 B | ||
| 4 -RTL Simulation - 1.mp4 | 19.2 MB | ||
| 4 -Synthesis.mp4 | 6.4 MB | ||
| 4 -Test Install.mp4 | 7.7 MB | ||
| 5 - Troubleshooting.html | 512 B | ||
| 5 -Gatesim.mp4 | 13 MB | ||
| 5 -RTL Simulation - 2.mp4 | 23.6 MB | ||
| 6 -Synthesis.mp4 | 27.9 MB | ||
| Bonus Resources.txt | 409.6 B | ||
| Get Bonus Downloads Here.url | 204.8 B | ||
| ▲ 37 total files | |||
RTL Finite State Machines in System Verilog
https://DevCourseWeb.com
Published 10/2024
Created by Ninja S
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Genre: eLearning | Language: English | Duration: 35 Lectures ( 56m ) | Size: 382 MB
Finite State Machines are a fundamental building block in digital hardware designs.
What you'll learn:
Learn the design pattern for Register Transfer Level (RTL) descriptions of Finite State Machines in Digital Hardware
Hands on simulation of RTL Finite State Machine with a self checking test bench
Synthesis of RTL Finite State Machines
Optimization of RTL Finite State Machine to reduce Latency
Requirements:
Background in Digital Hardware Design (Electrical or Computer Engineering)
Exposure to an HDL (Verilog or VHDL) would be helpful
Taken course RTL Fundamentals in System Verilog (Recommended)
| torrent name | size | uploader | age | seed | leech |
|---|---|---|---|---|---|
| 802 MB | freecoursewb | 2 months | 0 | 0 | |
| 1.4 GB | freecoursewb | 1 year | 8 | 0 |
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