| 001 Basic Crosstalk Glitch Example.mp4 | 9.1 MB | ||
| 001 Basic Crosstalk Glitch Example_en.vtt | 13.9 KB | ||
| 001 Crosstalk Delta Delay - Aggressor Victim Switching in Opposite Direction.mp4 | 8.3 MB | ||
| 001 Crosstalk Delta Delay - Aggressor Victim Switching in Opposite Direction_en.vtt | 12.6 KB | ||
| 001 High Routing Density.mp4 | 16.1 MB | ||
| 001 High Routing Density_en.vtt | 13.8 KB | ||
| 001 Impacts Of Glitch.mp4 | 8.5 MB | ||
| 001 Impacts Of Glitch_en.vtt | 14.3 KB | ||
| 001 Introduction To Power Supply Noise.mp4 | 10.7 MB | ||
| 001 Introduction To Power Supply Noise_en.vtt | 14.9 KB | ||
| 001 Introduction.mp4 | 6.4 MB | ||
| 001 Introduction_en.vtt | 11.1 KB | ||
| 001 Shielding.mp4 | 7.6 MB | ||
| 001 Shielding_en.vtt | 11.6 KB | ||
| 001 Single Victim Multiple Aggressors.mp4 | 9.4 MB | ||
| 001 Single Victim Multiple Aggressors_en.vtt | 13.1 KB | ||
| 001 Summary.mp4 | 6.4 MB | ||
| 001 Summary_en.vtt | 11.1 KB | ||
| 002 Dominant Lateral Capacitance.mp4 | 13.7 MB | ||
| 002 Dominant Lateral Capacitance_en.vtt | 13.1 KB | ||
| 002 Glitch Discharge With High Drive Strength NMOS Transistor.mp4 | 10 MB | ||
| 002 Glitch Discharge With High Drive Strength NMOS Transistor_en.vtt | 13.2 KB | ||
| 002 Impact of Crosstalk Delta Delay on Clock Skew.mp4 | 10.7 MB | ||
| 002 Impact of Crosstalk Delta Delay on Clock Skew_en.vtt | 12.8 KB | ||
| 002 Introduction to Safe and Unsafe Glitches.mp4 | 7.8 MB | ||
| 002 Introduction to Safe and Unsafe Glitches_en.vtt | 12.6 KB | ||
| 002 Introduction to Timing Window.mp4 | 9.5 MB | ||
| 002 Introduction to Timing Window_en.vtt | 12.1 KB | ||
| 002 Need of Decoupling Capacitors (DECAPS).mp4 | 14.5 MB | ||
| 002 Need of Decoupling Capacitors (DECAPS)_en.vtt | 15 KB | ||
| 002 Spacing.mp4 | 8.2 MB | ||
| 002 Spacing_en.vtt | 12.5 KB | ||
| 003 Drive Strength.mp4 | 16.2 MB | ||
| 003 Drive Strength_en.vtt | 15.1 KB | ||
| 003 Glitch Discharge With High Drive Strength PMOS Transistor.mp4 | 10.3 MB | ||
| 003 Glitch Discharge With High Drive Strength PMOS Transistor_en.vtt | 14.1 KB | ||
| 003 Introduction to Noise Margin.mp4 | 7.8 MB | ||
| 003 Introduction to Noise Margin_en.vtt | 10.8 KB | ||
| 003 Power Supply Noise With Multiple Instantiations.mp4 | 8.6 MB | ||
| 003 Power Supply Noise With Multiple Instantiations_en.vtt | 12 KB | ||
| 003 Setup Timing Analysis Using Real Clocks.mp4 | 10.9 MB | ||
| 003 Setup Timing Analysis Using Real Clocks_en.vtt | 13.1 KB | ||
| 003 Timing Window Formation.mp4 | 8.1 MB | ||
| 003 Timing Window Formation_en.vtt | 11.9 KB | ||
| 003 Tolerable Glitch Heights using DC Noise Margin.mp4 | 8.2 MB | ||
| 003 Tolerable Glitch Heights using DC Noise Margin_en.vtt | 12.2 KB | ||
| 004 Bucketization based on Timing Windows.mp4 | 11.1 MB | ||
| 004 Bucketization based on Timing Windows_en.vtt | 12.5 KB | ||
| 004 Factors Affecting Glitch Height - Spacing.mp4 | 8.7 MB | ||
| 004 Factors Affecting Glitch Height - Spacing_en.vtt | 13.5 KB | ||
| 004 Impact of Crosstalk Delta Delay on Setup Timing.mp4 | 12.5 MB | ||
| 004 Impact of Crosstalk Delta Delay on Setup Timing_en.vtt | 11.9 KB | ||
| 004 Noise Margin Voltage Parameters.mp4 | 9.1 MB | ||
| 004 Noise Margin Voltage Parameters_en.vtt | 10.7 KB | ||
| 004 Tolerable Glitch Heights using DC Noise Margin Continued.mp4 | 8.4 MB | ||
| 004 Tolerable Glitch Heights using DC Noise Margin Continued_en.vtt | 12.4 KB | ||
| 004 Voltage Droop And Ground Bounce.mp4 | 10.7 MB | ||
| 004 Voltage Droop And Ground Bounce_en.vtt | 12.6 KB | ||
| 005 AC Noise Margin.mp4 | 8 MB | ||
| 005 AC Noise Margin_en.vtt | 11.1 KB | ||
| 005 Crosstalk Delta Delay - Aggressor Victim Switching in Same Direction.mp4 | 7.5 MB | ||
| 005 Crosstalk Delta Delay - Aggressor Victim Switching in Same Direction_en.vtt | 11.7 KB | ||
| 005 Factors Affecting Glitch Height - Aggressor Drive Strength.mp4 | 9.7 MB | ||
| 005 Factors Affecting Glitch Height - Aggressor Drive Strength_en.vtt | 14.2 KB | ||
| 005 Final Glitch Calculation.mp4 | 10.2 MB | ||
| 005 Final Glitch Calculation_en.vtt | 12.5 KB | ||
| 005 Noise Margin Equation and Summary.mp4 | 9.8 MB | ||
| 005 Noise Margin Equation and Summary_en.vtt | 11.6 KB | ||
| 005 Power Mesh Solution.mp4 | 7.5 MB | ||
| 005 Power Mesh Solution_en.vtt | 10.2 KB | ||
| 006 Factors Affecting Glitch Height - Victim Drive Strength.mp4 | 8.3 MB | ||
| 006 Factors Affecting Glitch Height - Victim Drive Strength_en.vtt | 11.4 KB | ||
| 006 Hold Timing Analysis Using Real Clocks.mp4 | 9.7 MB | ||
| 006 Hold Timing Analysis Using Real Clocks_en.vtt | 13.1 KB | ||
| 006 Impact of Load on Glitch Height.mp4 | 8.9 MB | ||
| 006 Impact of Load on Glitch Height_en.vtt | 13 KB | ||
| 006 Lower Supply Voltage.mp4 | 9.2 MB | ||
| 006 Lower Supply Voltage_en.vtt | 13.4 KB | ||
| 007 Factors Affecting Glitch Height - Conclusion.mp4 | 10.2 MB | ||
| 007 Factors Affecting Glitch Height - Conclusion_en.vtt | 13.7 KB | ||
| 007 Impact of Crosstalk Delta Delay on Hold Timing.mp4 | 10.8 MB | ||
| 007 Impact of Crosstalk Delta Delay on Hold Timing_en.vtt | 11.1 KB | ||
| 007 Justification of Load Impact and Conclusion.mp4 | 8.4 MB | ||
| 007 Justification of Load Impact and Conclusion_en.vtt | 12.3 KB | ||
| Bonus Resources.txt | 409.6 B | ||
| Get Bonus Downloads Here.url | 204.8 B | ||
| ▲ 86 total files | |||
VSD - Signal Integrity
https://CourseHulu.com
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz
Language: English | Size: 406 MB | Duration: 6h 34m
VLSI - Real and practical steps to build chip with minimum Signal Integrity issues!!
What you'll learn
To Learn Chip Design with minimal Crosstalk in the circuits.
To Design a Chip with minimal errors.
Requirements
Basic of VLSI and Chip Design
Description
Performance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three.
Crosstalk is the interference caused due to communication between the circuits
| torrent name | size | uploader | age | seed | leech |
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Udemy - IMRaD-Q1 Paper Writing and Publishing with ChatGPT and AI '26 Posted by
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