Xilinx ISE update 11.5

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Xilinx ISE update 11.5

Год выпуска: 2010
Разработчик: Xilinx
Совместимость с Vista: неизвестно
Язык интерфейса: только английский
Таблэтка: Не требуется
Описание: Обновление для популярного пакета Xilinx ISE. Требует ISE 11.1+
Картинки и подробное описание - завтра.

Что нового (англ.)
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The following sections describe changes in ISE Design Suite for 11.5.

Introducing Production Support for Selected Spartan-6 and Virtex-6 Devices
Xilinx introduces production support for the following Spartan®-6 and Virtex®-6 devices in the 11.5 release:

Production Device Support
Spartan-6 LX16 (-2C, -2I) speed files

Virtex-6 LX240T (-1C, -1I, -2C, -2I) speed files

Virtex-6 LX130T (-1C, -2C) speed files

Support for future Spartan-6 and Virtex-6 production devices

Updated speed files for all other Spartan-6 and Virtex-6 production devices

Note: Production devices will still have speed files labeled, in the software, as "Preliminary". For the latest status on production devices, please check the following data sheets.

Virtex-6: Virtex-6 FPGA Data Sheet: DC and Switching Characteristics - See table entitled "Virtex-6 Device Production Software and Speed Specification Release"

Spartan-6: Spartan-6 FPGA Data Sheet: DC and Switching Characteristics - See table entitled "Spartan-6 Device Production Software and Speed Specification Release"

What's New in Logic Design Tools
This release includes several improvements to Virtex-6 and Spartan-6 design tools to support production silicon including the following.

Design Rule Checking (DRC) improvements - New DRC Checks for Virtex-6 MMCM module.

Minimum frequency for VCO changed to 600 MHz (from 400 MHz).

Fractional divide is disabled for CLKFBOUT.

Multi-Corner Timing Analysis for Spartan-6. The benefits of multi-corner timing analysis are:

Faster fabric performance due to decreased clock skew. On average , Spartan-6 is seeing 5% faster performance compared to 11.4.

Faster I/O performance due to decrease min/max variation.

What's New in IP
For Virtex-6 designs, these IP updates are required. If you are using the following IP in a Virtex-6 design, each core should be regenerated, using these newer versions, and the design re-implemented. If you are using EDK flows, even with families other than Virtex-6, the updated IP cores may be incorporated automatically into your designs. This may produce results that differ from previous 11.x versions, and the design should be re-checked for validity.

10 Gigabit Ethernet MAC

Gigabit Ethernet 1000BASE-X Aurora 64b66b

Aurora 8b10b

Clocking Wizard

CPRI

Multi-Port Memory Controller (MPMC)

OBSAI

RXAUI

Serial RapidIO

SPI-3 Link Layer

SPI-4.2 Lite

Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC

Virtex-6 GTX Wizard

Virtex-6 Integrated Block for PCI Express

XAUI

Video Scaler

Video Frame Buffer Controller (VFBC) PIM
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