| 1. Agenda.mp4 | 624.9 KB | ||
| 1. Agenda.srt | 409.6 B | ||
| 1. Course Overview.mp4 | 15.3 MB | ||
| 1. Course Overview.srt | 3.7 KB | ||
| 10. Adapter code with Protocol Specific ports P1.mp4 | 30.6 MB | ||
| 10. Adapter code with Protocol Specific ports P1.srt | 5.9 KB | ||
| 10. Adding Agent.mp4 | 7.1 MB | ||
| 10. Adding Agent.srt | 1.3 KB | ||
| 10. Components of Register model P2.mp4 | 19.6 MB | ||
| 10. Components of Register model P2.srt | 6.6 KB | ||
| 10. Coverage analysis P1.mp4 | 40 MB | ||
| 10. Coverage analysis P1.srt | 7 KB | ||
| 10. Design Code.html | 2.2 KB | ||
| 10. Peek and Poke P1.mp4 | 29.4 MB | ||
| 10. Peek and Poke P1.srt | 5.6 KB | ||
| 11. Adapter code with Protocol Specific ports P2.mp4 | 9.7 MB | ||
| 11. Adapter code with Protocol Specific ports P2.srt | 1.9 KB | ||
| 11. Adding Register Model.mp4 | 61.5 MB | ||
| 11. Adding Register Model.srt | 9.5 KB | ||
| 11. Components of Register model P3.mp4 | 6.8 MB | ||
| 11. Components of Register model P3.srt | 2.3 KB | ||
| 11. Coverage analysis P2.mp4 | 19.1 MB | ||
| 11. Coverage analysis P2.srt | 3.6 KB | ||
| 11. Peek and Poke P2.mp4 | 10.1 MB | ||
| 11. Peek and Poke P2.srt | 1.3 KB | ||
| 11. Testbench Code.html | 22 KB | ||
| 12. A81.html | 204.8 B | ||
| 12. Adding env + uvm test top + testbench top.mp4 | 49.9 MB | ||
| 12. Adding env + uvm test top + testbench top.srt | 7.4 KB | ||
| 12. Coverage analysis P3.mp4 | 15.2 MB | ||
| 12. Coverage analysis P3.srt | 2.2 KB | ||
| 12. Coverage computation for memory P1.mp4 | 9.9 MB | ||
| 12. Coverage computation for memory P1.srt | 1.4 KB | ||
| 12. Design Code.html | 716.8 B | ||
| 12. Notes.html | 307.2 B | ||
| 12. Summary.mp4 | 16.7 MB | ||
| 12. Summary.srt | 4.5 KB | ||
| 13. A82.html | 204.8 B | ||
| 13. Coverage computation for memory P2.mp4 | 49.9 MB | ||
| 13. Coverage computation for memory P2.srt | 7.2 KB | ||
| 13. Design Code.html | 716.8 B | ||
| 13. Executing Code.mp4 | 15.4 MB | ||
| 13. Executing Code.srt | 1.7 KB | ||
| 13. Slides.html | 1 KB | ||
| 13. Testbench Code.html | 9.4 KB | ||
| 13. Typical Learning Path.mp4 | 7.4 MB | ||
| 13. Typical Learning Path.srt | 3.5 KB | ||
| 14. A31.html | 204.8 B | ||
| 14. A51.html | 204.8 B | ||
| 14. Design Code.html | 512 B | ||
| 14. Testbench Code.html | 13 KB | ||
| 14. Understanding different types of registers.mp4 | 11.6 MB | ||
| 14. Understanding different types of registers.srt | 5 KB | ||
| 15. Implementation of Register in Verification Environmnet P1.mp4 | 51.1 MB | ||
| 15. Implementation of Register in Verification Environmnet P1.srt | 9.2 KB | ||
| 15. Testbench Code.html | 11.5 KB | ||
| 15. Understanding Desired and Mirrored Values.mp4 | 20.5 MB | ||
| 15. Understanding Desired and Mirrored Values.srt | 5.8 KB | ||
| 15. run.do.html | 204.8 B | ||
| 16. Different register methods.mp4 | 6.8 MB | ||
| 16. Different register methods.srt | 3.1 KB | ||
| 16. Implementation of Register in Verification Environmnet P2.mp4 | 55.8 MB | ||
| 16. Implementation of Register in Verification Environmnet P2.srt | 9.5 KB | ||
| 17. Alternate way of adding configure function.mp4 | 7.7 MB | ||
| 17. Alternate way of adding configure function.srt | 1.9 KB | ||
| 17. Working with Desired Value.mp4 | 67 MB | ||
| 17. Working with Desired Value.srt | 11.8 KB | ||
| 18. Summary Configure function.mp4 | 9.4 MB | ||
| 18. Summary Configure function.srt | 2.8 KB | ||
| 18. Testbench Code.html | 8.7 KB | ||
| 19. Implementation of Register in Verification Environmnet P3.mp4 | 44.1 MB | ||
| 19. Implementation of Register in Verification Environmnet P3.srt | 8 KB | ||
| 19. Working with Mirrored Value.mp4 | 50.9 MB | ||
| 19. Working with Mirrored Value.srt | 7.3 KB | ||
| 2. Adding Register Block P1.mp4 | 25.5 MB | ||
| 2. Adding Register Block P1.srt | 6 KB | ||
| 2. Agenda.mp4 | 6.1 MB | ||
| 2. Agenda.srt | 1.5 KB | ||
| 2. Type of access methods p1 Frontdoor.mp4 | 10.4 MB | ||
| 2. Type of access methods p1 Frontdoor.srt | 3.4 KB | ||
| 2. Types of Predictor Implicit Predictor.mp4 | 27.6 MB | ||
| 2. Types of Predictor Implicit Predictor.srt | 7.3 KB | ||
| 2. Understanding Design P1.mp4 | 18.1 MB | ||
| 2. Understanding Design P1.srt | 5.4 KB | ||
| 2. Understanding Design for Explicit Predictor.mp4 | 9.5 MB | ||
| 2. Understanding Design for Explicit Predictor.srt | 3.6 KB | ||
| 2. Understanding Design.mp4 | 14.6 MB | ||
| 2. Understanding Design.srt | 2.7 KB | ||
| 2. Usage of adapter.mp4 | 4.5 MB | ||
| 2. Usage of adapter.srt | 1.6 KB | ||
| 20. Code.html | 1.1 KB | ||
| 20. Testbench Code.html | 9.2 KB | ||
| 21. Slides.html | 409.6 B | ||
| 21. Understanding predict and mirror.mp4 | 32.5 MB | ||
| 21. Understanding predict and mirror.srt | 5.8 KB | ||
| 22. Adding Register with two fields.mp4 | 41.7 MB | ||
| 22. Adding Register with two fields.srt | 8.3 KB | ||
| 22. Demonstration.mp4 | 55.5 MB | ||
| 22. Demonstration.srt | 7.8 KB | ||
| 23. Code.html | 1.4 KB | ||
| 23. Testbench Code.html | 9 KB | ||
| 24. Adding Register with reserved bits.mp4 | 22.1 MB | ||
| 24. Adding Register with reserved bits.srt | 5.3 KB | ||
| 24. Single Read and Write Transaction.mp4 | 32.1 MB | ||
| 24. Single Read and Write Transaction.srt | 6.1 KB | ||
| 25. Code.html | 1.2 KB | ||
| 25. Multiple Read and Write Transaction.mp4 | 25.4 MB | ||
| 25. Multiple Read and Write Transaction.srt | 4.4 KB | ||
| 26. Different Access Policy P1.mp4 | 10.2 MB | ||
| 26. Different Access Policy P1.srt | 4.2 KB | ||
| 26. Testbench Code.html | 9.4 KB | ||
| 27. Different Access Policy P2.mp4 | 57.6 MB | ||
| 27. Different Access Policy P2.srt | 7.9 KB | ||
| 27. Using randomize.mp4 | 26.6 MB | ||
| 27. Using randomize.srt | 6.2 KB | ||
| 28. Different Access Policy P3.mp4 | 44.9 MB | ||
| 28. Different Access Policy P3.srt | 5.9 KB | ||
| 28. Testbench Code.html | 8.5 KB | ||
| 29. Different Access Policy P4.mp4 | 58.9 MB | ||
| 29. Different Access Policy P4.srt | 7.8 KB | ||
| 29. Understanding Reset Methods.mp4 | 13.4 MB | ||
| 29. Understanding Reset Methods.srt | 3.7 KB | ||
| 3. Adding Register Block P2.mp4 | 37.5 MB | ||
| 3. Adding Register Block P2.srt | 5.4 KB | ||
| 3. Advantage of UVM RAL P1.mp4 | 25.5 MB | ||
| 3. Advantage of UVM RAL P1.srt | 8.8 KB | ||
| 3. Building DRV + MON + SCO + AGENT.mp4 | 46.5 MB | ||
| 3. Building DRV + MON + SCO + AGENT.srt | 8.4 KB | ||
| 3. Building Verification env P1.mp4 | 50.9 MB | ||
| 3. Building Verification env P1.srt | 12.1 KB | ||
| 3. Type of access methods p2 Backdoor.mp4 | 8.3 MB | ||
| 3. Type of access methods p2 Backdoor.srt | 3.8 KB | ||
| 3. Types of Predictor Explicit Predictor.mp4 | 4.2 MB | ||
| 3. Types of Predictor Explicit Predictor.srt | 1.3 KB | ||
| 3. Typical flow.mp4 | 5.6 MB | ||
| 3. Typical flow.srt | 2.1 KB | ||
| 3. Understand Design P2.mp4 | 26.9 MB | ||
| 3. Understand Design P2.srt | 7.2 KB | ||
| 30. Demonstration.mp4 | 58.7 MB | ||
| 30. Demonstration.srt | 8.1 KB | ||
| 30. Notes.html | 1.4 KB | ||
| 31. Adding Memory P1.mp4 | 7.1 MB | ||
| 31. Adding Memory P1.srt | 2.6 KB | ||
| 31. Testbench Code.html | 9.7 KB | ||
| 32. Adding Memory P2.mp4 | 35.2 MB | ||
| 32. Adding Memory P2.srt | 6.1 KB | ||
| 32. Connecting reset methods to DUT.mp4 | 35.3 MB | ||
| 32. Connecting reset methods to DUT.srt | 5.7 KB | ||
| 33. Code.html | 716.8 B | ||
| 33. Testbench Code.html | 8.9 KB | ||
| 34. A41.html | 204.8 B | ||
| 34. Slides.html | 409.6 B | ||
| 35. A11.html | 204.8 B | ||
| 36. A12.html | 204.8 B | ||
| 4. Adding Register Block P3.mp4 | 61.8 MB | ||
| 4. Adding Register Block P3.srt | 9.2 KB | ||
| 4. Advantage of UVM RAL P2.mp4 | 12.9 MB | ||
| 4. Advantage of UVM RAL P2.srt | 3.2 KB | ||
| 4. Building Register model.mp4 | 70 MB | ||
| 4. Building Register model.srt | 10.6 KB | ||
| 4. Building Verification env P2.mp4 | 26.4 MB | ||
| 4. Building Verification env P2.srt | 7.1 KB | ||
| 4. Building Verification environment P1.mp4 | 33.5 MB | ||
| 4. Building Verification environment P1.srt | 9 KB | ||
| 4. Frontdoor Demonstration.mp4 | 33.4 MB | ||
| 4. Frontdoor Demonstration.srt | 5.8 KB | ||
| 4. Structure of uvm_reg_bus_op struct.mp4 | 7.1 MB | ||
| 4. Structure of uvm_reg_bus_op struct.srt | 2.2 KB | ||
| 4. Types of Predictor Passive Predictor.mp4 | 17.8 MB | ||
| 4. Types of Predictor Passive Predictor.srt | 5.2 KB | ||
| 5. Adding Register sequence Single Transaction.mp4 | 56 MB | ||
| 5. Adding Register sequence Single Transaction.srt | 7.5 KB | ||
| 5. Advantage of UVM RAL P3.mp4 | 8.2 MB | ||
| 5. Advantage of UVM RAL P3.srt | 1.8 KB | ||
| 5. Building Verification env P3.mp4 | 21.3 MB | ||
| 5. Building Verification env P3.srt | 5.5 KB | ||
| 5. Building Verification environment P2.mp4 | 36.8 MB | ||
| 5. Building Verification environment P2.srt | 7.3 KB | ||
| 5. Code.html | 2.4 KB | ||
| 5. Complete flow.mp4 | 14.3 MB | ||
| 5. Complete flow.srt | 3.6 KB | ||
| 5. Slide.html | 1 KB | ||
| 5. Testbench Code.html | 8.9 KB | ||
| 6. Adding Register sequence Multiple Transactions.mp4 | 30.4 MB | ||
| 6. Adding Register sequence Multiple Transactions.srt | 4.8 KB | ||
| 6. Advantage of UVM RAL P4.mp4 | 11.5 MB | ||
| 6. Advantage of UVM RAL P4.srt | 2.6 KB | ||
| 6. Building Register model P1.mp4 | 33.7 MB | ||
| 6. Building Register model P1.srt | 7.5 KB | ||
| 6. Building Verification env P4.mp4 | 5 MB | ||
| 6. Building Verification env P4.srt | 1.5 KB | ||
| 6. Driver Sequencer Communication.mp4 | 49.5 MB | ||
| 6. Driver Sequencer Communication.srt | 9.2 KB | ||
| 6. Fundamentals of Backdoor access.mp4 | 14.9 MB | ||
| 6. Fundamentals of Backdoor access.srt | 6.1 KB | ||
| 6. Slides.html | 409.6 B | ||
| 6. Understanding reg2bus.mp4 | 45.6 MB | ||
| 6. Understanding reg2bus.srt | 10.6 KB | ||
| 7. A21.html | 204.8 B | ||
| 7. Building Register model P2.mp4 | 39.8 MB | ||
| 7. Building Register model P2.srt | 9.7 KB | ||
| 7. Code.html | 3.6 KB | ||
| 7. Demonstration.mp4 | 75.1 MB | ||
| 7. Demonstration.srt | 10.9 KB | ||
| 7. Design Code.html | 512 B | ||
| 7. Testing Code.mp4 | 20.6 MB | ||
| 7. Testing Code.srt | 2 KB | ||
| 7. Understanding bus2reg.mp4 | 10 MB | ||
| 7. Understanding bus2reg.srt | 3.4 KB | ||
| 7. When to use RAL in Verification environment.mp4 | 22.3 MB | ||
| 7. When to use RAL in Verification environment.srt | 6.2 KB | ||
| 8. Adapter code with native memory ports P1.mp4 | 32.5 MB | ||
| 8. Adapter code with native memory ports P1.srt | 6.5 KB | ||
| 8. Adding testbench top.mp4 | 11.6 MB | ||
| 8. Adding testbench top.srt | 3.1 KB | ||
| 8. Code.html | 1 KB | ||
| 8. Design Code.html | 716.8 B | ||
| 8. Testbench Code.html | 11.1 KB | ||
| 8. Understanding Design.mp4 | 13.4 MB | ||
| 8. Understanding Design.srt | 3.6 KB | ||
| 9. Adapter code with native memory ports P2.mp4 | 19.6 MB | ||
| 9. Adapter code with native memory ports P2.srt | 3.2 KB | ||
| 9. Adding Driver + Sequencer.mp4 | 37.9 MB | ||
| 9. Adding Driver + Sequencer.srt | 7.4 KB | ||
| 9. Burst Transactions.mp4 | 71.4 MB | ||
| 9. Burst Transactions.srt | 11.1 KB | ||
| 9. Components of Register model P1.mp4 | 27 MB | ||
| 9. Components of Register model P1.srt | 9.8 KB | ||
| 9. Testbench Code.html | 12 KB | ||
| 9. Testing DUT.mp4 | 17.4 MB | ||
| 9. Testing DUT.srt | 2.5 KB | ||
| Bonus Resources.txt | 409.6 B | ||
| Get Bonus Downloads Here.url | 204.8 B | ||
| ▲ 250 total files | |||
UVM for Verification Part 3:Register Abstraction Layer (RAL)
https://DevCourseWeb.com
Last updated 3/2023
Created by Kumar Khandagle
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Genre: eLearning | Language: English + srt | Duration: 140 Lectures ( 7h 10m ) | Size: 2.56 GB
Step by Step Guide from Scratch
What you'll learn
Using UVM RAL for verification of DUT Registers and Memories
Understanding different Register as well memories methods
Implementing Frontdoor and Backdoor access methods
Implementing Implicit and Explicit Predictor
Coverage Computation for Register and Memories
Requirements
Basic understanding of Verilog, SystemVerilog, and UVM
| torrent name | size | uploader | age | seed | leech |
|---|---|---|---|---|---|
| 2.9 GB | freecoursewb | 3 years | 0 | 0 |
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