| 001 1-Introduction-to-FPGA.pdf | 2.3 MB | ||
| 001 16-Simulate-and-implement-SOPC-Design.pdf | 1.8 MB | ||
| 001 17-Reading-Data-from-Peripherals.pdf | 469.7 KB | ||
| 001 18-UART-SDRAM-Python.pdf | 2.2 MB | ||
| 001 2-FPGA-Testing.pdf | 1.1 MB | ||
| 001 20-Image-Processing-using-FPGA.pdf | 2 MB | ||
| 001 21-Challenges-in-using-FPAA-FPGA-in-Mixed-Signal-Technology.pdf | 673.2 KB | ||
| 001 22-Protoflex.pdf | 2.4 MB | ||
| 001 23-Reconfigurable-Hardware.pdf | 3 MB | ||
| 001 24-Wordcount-using-MapReduce-for-FPGA.pdf | 1.2 MB | ||
| 001 25-FPGA-implementation-of-DSP-Circuits.pdf | 963.4 KB | ||
| 001 26-Reversible-Logic-Circuits.pdf | 3.7 MB | ||
| 001 27-FPGA-implementation-of-Divider-in-Finite-Field.pdf | 642.1 KB | ||
| 001 28-Principles-of-PLI.pdf | 391.1 KB | ||
| 001 29-Spartan-FPGA-implementation.pdf | 942.6 KB | ||
| 001 3-FPGA-Design-Flows-Design-Tools.pdf | 882.7 KB | ||
| 001 30-Programmable-Chips-and-Boards.pdf | 2.5 MB | ||
| 001 31-Memristive-FPGA.pdf | 3.1 MB | ||
| 001 32-Mentor-Graphics-Tools-Guidelines.pdf | 1.1 MB | ||
| 001 4-FPGA-Design-using-Verilog-Introduction.pdf | 1.6 MB | ||
| 001 Challenges in using FPAA FPGA in Mixed Signal Technology.mp4 | 27.3 MB | ||
| 001 FPGA Design Flows & Design Tools.mp4 | 272.6 MB | ||
| 001 FPGA Testing.mp4 | 93.5 MB | ||
| 001 FPGA implementation of DSP Circuits.mp4 | 142.7 MB | ||
| 001 FPGA implementation of Divider in Finite Field.mp4 | 53.1 MB | ||
| 001 Image Processing using FPGA.mp4 | 171.3 MB | ||
| 001 Introduction to FPGA (Field Programmable Gate Arrays).mp4 | 183.2 MB | ||
| 001 Introduction to FPGA Design using Verilog.mp4 | 110.1 MB | ||
| 001 Memristive FPGA.mp4 | 205.6 MB | ||
| 001 Mentor Graphics Tools & Guidelines.mp4 | 175.8 MB | ||
| 001 Principles of PLI.mp4 | 69.3 MB | ||
| 001 Programmable Chips and Boards.mp4 | 156.1 MB | ||
| 001 Protoflex.mp4 | 117.9 MB | ||
| 001 Reading Data from Peripherals.mp4 | 50.6 MB | ||
| 001 Reconfigurable Hardware.mp4 | 200.2 MB | ||
| 001 Reversible Logic Circuits.mp4 | 136.8 MB | ||
| 001 Script execution in Quartus and ModelSim NIOS.mp4 | 96.7 MB | ||
| 001 Simulate and Implement SOPC Design.mp4 | 188.9 MB | ||
| 001 Spartan FPGA implementation.mp4 | 62.1 MB | ||
| 001 UART SDRAM Python.mp4 | 126.4 MB | ||
| 001 Wordcount using MapReduce for FPGA.mp4 | 104.5 MB | ||
| 002 5-FPGA-Design-using-Verilog-Verilog-overview.pdf | 558.1 KB | ||
| 002 Verilog overview.mp4 | 106.2 MB | ||
| 003 6-FPGA-Design-using-Verilog-Data-Types.pdf | 420.9 KB | ||
| 003 Data Types.mp4 | 92.8 MB | ||
| 004 7-FPGA-Design-using-Verilog-Procedural-Assignments.pdf | 519.8 KB | ||
| 004 Procedural Assignments.mp4 | 114.1 MB | ||
| 005 8-FPGA-Design-using-Verilog-VHDL-Design-using-Verilog.pdf | 1.1 MB | ||
| 005 VHDL Design using Verilog.mp4 | 96.7 MB | ||
| 006 9-FPGA-Design-using-Verilog-Visual-Verification-of-Designs.pdf | 680.9 KB | ||
| 006 Visual Verification of Designs.mp4 | 158 MB | ||
| 007 10-FPGA-Design-using-Verilog-Finite-State-Machines-part-1.pdf | 901.6 KB | ||
| 007 Finite State Machines - part 1.mp4 | 126.2 MB | ||
| 008 11-FPGA-Design-using-Verilog-Finite-State-Machines-part-2.pdf | 740.1 KB | ||
| 008 Finite State Machines - part 2.mp4 | 146 MB | ||
| 009 12-FPGA-Design-using-Verilog-Design-Examples.pdf | 910.5 KB | ||
| 009 Design Examples.mp4 | 216.1 MB | ||
| 010 13-FPGA-Design-using-Verilog-Test-Benches.pdf | 900.1 KB | ||
| 010 Test Benches.mp4 | 97.7 MB | ||
| 011 14-FPGA-Design-using-Verilog-SystemVerilog-for-Synthesis.pdf | 347.5 KB | ||
| 011 SystemVerilog for Synthesis.mp4 | 95.4 MB | ||
| 012 15-FPGA-Design-using-Verilog-Packages-Interfaces.pdf | 314.3 KB | ||
| 012 Packages & Interfaces.mp4 | 40.2 MB | ||
| Bonus Resources.txt | 409.6 B | ||
| Get Bonus Downloads Here.url | 204.8 B | ||
| ▲ 65 total files | |||
FPGA (Field-Programmable Gate Array) Design & Implementation
https://DevCourseWeb.com
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Genre: eLearning | Language: English + srt | Duration: 32 lectures (11h 26m) | Size: 2.96 GB
Become FPGA Design Engineer. Learn FPGA Design Engineering, Design Flows & Tools, FPGA DSP Circuits, Protoflex, PLI etc
What you'll learn
Gain end-to-end knowledge of FPGA design engineering & implementation
Acquire skills to become FPGA Design & Implementation Engineer
Learn FPGA Design flows & design tools
Understand and implement FPGA Design using Verilog
Learn FPGA Testing
Simulate and implement SOPC Design
Learn how to read data from Peripherals
Learn FPGA implementation of DSP Circuits
Define Wordcount using MapReduce for FPGA
Describe Protoflex and Reconfigurable Hardware
Understand challenges in using FPAA FPGA in Mixed Signal Technology
Get knowledge of Mentor Graphics Tools & Guidelines
Define & execute Spartan FPGA and Memristive FPGA
Requirements
Enthusiasm and determination to make your mark on the world!
| torrent name | size | uploader | age | seed | leech |
|---|---|---|---|---|---|
| 2.2 GB | freecoursewb | 4 months | 0 | 0 | |
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Udemy - FPGA Timings P2 - Clock Domain Crossing(CDC) with Vivado 2024 Posted by
freecoursewb in Other
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1.8 GB | freecoursewb | 1 year | 2 | 1 |
|
Udemy - Digital IC - FPGA Design P3 - Common Used Hardware Architectures Posted by
freecoursewb in Other
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1.1 GB | freecoursewb | 1 year | 0 | 0 |
| 1.9 GB | freecoursewb | 3 years | 1 | 4 | |
| 638.4 MB | freecoursewb | 3 years | 4 | 0 |
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