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Udemy - VLSI DFT Basics - From Industry Perspective

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Added 9 months ago by freecoursewb in Other
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Udemy - VLSI DFT Basics - From Industry Perspective (Size: 1.4 GB)
  1 - Basic DFT Implementation Flows used in Industry.mp4 45.2 MB
  1 - Chip Design Flow-RTL to GDSII.mp4 120.6 MB
  1 - Conclusion.mp4 6 MB
  1 - Introduction to Basics of Testing Methods Section.mp4 4.3 MB
  1 - Introduction.mp4 123.7 MB
  1 - Manufacturing Defects.mp4 44.4 MB
  2 - Basic SCAN Insertion Flow.mp4 85.2 MB
  2 - Fault Modeling and Types.mp4 33.5 MB
  2 - Introduction of Basics of Testing Methods.mp4 4.3 MB
  2 - Purpose of Testing.mp4 71.6 MB
  3 - Building Blocks of Chip.mp4 55 MB
  3 - MBIST Insertion Flow.mp4 23.2 MB
  3 - Stuck-at Fault Model.mp4 26 MB
  3 - Types of Testing.mp4 149 MB
  4 - BSD Insertion Flow.mp4 9.9 MB
  4 - Memory BIST (MBIST).mp4 101.1 MB
  4 - Transition Fault Model.mp4 22 MB
  5 - Analog IP Test Mode Insertion Flow.mp4 42.1 MB
  5 - Boundary Scan Diagnosis (BSD).mp4 122.8 MB
  5 - IDDQ Fault Model.mp4 17.6 MB
  6 - Different Tools Usage in DFT.mp4 18.5 MB
  6 - Path Delay Fault Model.mp4 21.9 MB
  6 - SCAN.mp4 257.3 MB
  7 - Analog IPs Testing.mp4 56.6 MB
  7 - Cell-Aware Fault Model.mp4 7.3 MB
  Bonus Resources.txt 102.4 B
  Get Bonus Downloads Here.url 204.8 B
  ▲ 27 total files

Description


VLSI DFT Basics: From Industry Perspective

https://WebToolTip.com

Published 9/2025
Created by Awais Hussain
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Level: Beginner | Genre: eLearning | Language: English | Duration: 25 Lectures ( 3h 5m ) | Size: 1.43 GB

The purpose of DFT testing in VLSI along with industry standard DFT implementation flows

What you'll learn
The purpose of DFT testing in VLSI and its role in reliable chip manufacturing
The chip design flow and how DFT integrates into chip design flow
Common manufacturing defects and fault models (stuck-at, transition, IDDQ, path delay)
Introduction to core DFT techniques including SCAN, MBIST, and Boundary Scan
How analog IPs are tested — a topic rarely covered in other courses
Never taught before industry-standard DFT implementation flow used in real chip projects

Requirements
Basic digital logic design knowledge (logic gates, flip-flops, combinational vs. sequential circuits)
Familiarity with HDL (Verilog or VHDL) at an introductory level
Basic awareness of the VLSI design flow (RTL to GDSII)
General understanding of semiconductor basics (what is a chip, role of transistors, CMOS)
Comfortable with timing concepts such as setup/hold, clock, and reset

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