Udemy - VLSI Physical Design - PnR with Cadence

VLSI Physical Design: PnR with Cadence
https://WebToolTip.com
Published 3/2026

Created by Electronics Zone

MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch

Level: All Levels | Genre: eLearning | Language: English | Duration: 10 Lectures ( 3h 58m ) | Size: 2 GB
From Netlist to GDSII: Learn Floorplanning, Placement, CTS, Routing, and Timing Closure using Industry-Standard EDA Tool
What you'll learn

✓ Complete PnR Flow: Understand the step-by-step process of Physical Design from Netlist to GDSII.

✓ Tool Proficiency: Gain hands-on experience with industry-standard Cadence PnR tools.

✓ Floorplanning: Master techniques for die area estimation, I/O placement, and macro placement to optimize chip layout.

✓ Power Planning: Design robust power grids (power stripes/rings) to mitigate IR drop and electromigration.

✓ Placement Optimization: Perform standard cell placement and resolve placement-related congestion and timing issues.

✓ Timing Analysis: Analyze static timing reports and apply optimization techniques to fix setup and hold violations.

✓ Clock Tree Synthesis (CTS): Build balanced clock trees with low latency and skew.

✓ Routing: Execute global and detailed routing to connect all nets without design rule check (DRC) violations.

✓ Chip Finishing: Execute final steps including metal fill insertion and generating the final GDSII stream file for tape-out.
Requirements

● Basic VLSI Knowledge: Familiarity with the CMOS technology and the standard ASIC design flow (Frontend vs. Backend).

● Digital Electronics: Understanding of basic logic gates, flip-flops, and combinational logic.

● Linux Basics: Comfort with the Linux command line (navigating directories, editing files using vi/vim) as most EDA tools run on Linux.Linux Basics: Comfort with the Linux command line (navigating directories, editing files using vi/vim) as most EDA tools run on Linux.

● Timing Concepts (Recommended): A basic understanding of Static Timing Analysis (STA) concepts like setup time, hold time, and clock skew is helpful but not mandatory, as these will be reviewed.